SI4463 Datasheet, PDF (19/53 Pages) Silicon Laboratories – HIGH-PERFORMANCE

Si4463/61/60-C
Table 10. Operating State Response Time and Current Consumption
State/Mode
Shutdown State
Response Time to
TX
RX
15 ms
15 ms
Current in State
/Mode
30 nA
Standby State
Sleep State
SPI Active State
Ready State
TX Tune State
RX Tune State
440 µs
440 µs
340 µs
100 µs
58 µs
—
440 µs
440 µs
340 µs
100 µs
—
60 µs
40 nA
740 nA
1.35 mA
1.8 mA
7.8 mA
7.6 mA
TX State
—
100 µs
18 mA @ +10 dBm
RX State
100 µs
75 µs
10.9 or 13.7 mA
Note: TXRX and RXTX state transition timing can be reduced to 70 µs if using Zero-IF mode.
Figure 7 shows the POR timing and voltage requirements. The power consumption (battery life) depends on the
duty cycle of the application or how often the part is in either Rx or Tx state. In most applications the utilization of
the standby state will be most advantageous for battery life but for very low duty cycle applications shutdown will
have an advantage. For the fastest timing the next state can be selected in the START_RX or START_TX API
commands to minimize SPI transactions and internal MCU processing.
3.3.1. Power on Reset (POR)
A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this
process, VDD must ramp within 1ms and must remain applied to the device for at least 10 ms. If VDD is removed,
then it must stay below 0.15 V for at least 10 ms before being applied again. See Figure 7 and Table 11 for details.
V_DD
V_{R RH}
V_{R RL}
t_SR t_PORH
Figure 7. POR Timing Diagram
Time
Rev 1.0
19