SI4706-D50 Datasheet, PDF (24/36 Pages) Silicon Laboratories – HIGH-PERFORMANCE FM AND RDS/RBDS RECEIVER

Si4706-D50
1.E+00
Decoder Failure Probability
1.E-01
1.E-02
1.E-03
RDS Standard Limits
Si4706 RDS Decoder
1.E-04
0
1
2
3
4
5
6
Eb/N0
Figure 14. Si4706 Preliminary Decoder Performance
4.14. Reference Clock
The Si4706 reference clock is programmable,
supporting RCLK frequencies in Table 10. Refer to
Table 3, “DC Characteristics” on page 5 for switching
voltage levels and Table 10, “Reference Clock and
Crystal Characteristics” on page 14 for frequency
tolerance information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 15. This mode is enabled using the
POWER_UP command. Refer to Refer to “AN332:
Si47xx Programming Guide”.
The Si4706 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4706 is performing the seek/tune function,
the crystal oscillator may experience jitter, which may
result in mistunes, false stops, and/or lower SNR.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4706 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
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Rev. 1.0