SI4706-D50 Datasheet, PDF (10/36 Pages) Silicon Laboratories – HIGH-PERFORMANCE FM AND RDS/RBDS RECEIVER

Si4706-D50
Table 7. Digital Audio Interface Characteristics
(V_A = 2.7 to 5.5 V, V_D = 1.62 to 3.6 V, T_A = –20 to 85 °C)
Parameter
DCLK Cycle Time
DCLK Pulse Width High
DCLK Pulse Width Low
DFS Setup Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
DOUT Propagation Delay from DCLK Falling
Edge
Symbol Test Condition Min
t_DCT
26
t_DCH
10
t_DCL
10
t_SU:DFS
5
t_HD:DFS
5
t_PD:DOUT
0
Typ Max Unit
— 1000 ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
12
ns
DCLK
DFS
DOUT
t_DCH
t_DCL
t_DCT
t_HD:DFS
t_SU:DFS
t_PD:OUT
Figure 6. Digital Audio Interface Timing Parameters, I²S Mode
10
Rev. 1.0