ISL6266 Datasheet, PDF (21/31 Pages) Intersil Corporation – Precision Two/One-phase CORE Voltage Regulator

ISL6266, ISL6266A
Overcurrent protection is tied to the voltage droop, which is
determined by the resistors selected as described in
“Component Selection and Application” on page 22. After
the load-line is set, the OCSET resistor can be selected to
detect overcurrent at any level of droop voltage. An
overcurrent fault will occur when the load current exceeds
the overcurrent setpoint voltage while the regulator is in a
2-phase mode. While the regulator is in a 1-phase mode of
operation, the overcurrent setpoint is automatically reduced
to 50% of two-phase overcurrent level, and the fast-trip
way-overcurrent set point is reduced to 66%. For
overcurrents less than 2.5 times the OCSET level, the over-
load condition must exist for 120µs in order to trip the OC
fault latch. This is shown in Figure 25.
For over-loads exceeding 2.5 times the set level, the PWM
outputs will immediately shut off and PGOOD goes low to
maximize protection due to hard shorts.
In addition, excessive phase imbalance (for example, due to
gate driver failure) will be detected in two-phase operation
and the controller will be shut-down 1ms after detection of
the excessive phase current imbalance. The phase
imbalance is detected by the voltage on the ISEN pins if the
difference is greater than 9mV.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VID set value by
300mV or more, a fault will latch after 1ms in that condition,
turning the PWM outputs off and pulling PGOOD to ground.
Note that most practical core regulators will have the
overcurrent set to trip before the -300mV undervoltage limit.
There are two levels of overvoltage protection and response.
1. For output voltage exceeding the set value by +200mV
for 1ms, a fault is declared. All of the above faults have
the same action taken: PGOOD is latched low and the
upper and lower power MOSFETs are turned off so that
inductor current will decay through the MOSFET(s) body
diode(s). This condition can be reset by bringing VR_ON
low or by bringing VDD below 4V. When these inputs are
returned to their high operating levels, a soft-start will
occur.
2. The second level of overvoltage protection behaves
differently (see Figure 26). If the output exceeds 1.7V, an
OV fault is immediately declared, PGOOD is latched low
and the low-side MOSFETs are turned on. The low-side
MOSFETs will remain on until the output voltage is pulled
down below about 0.85V, at which time all MOSFETs are
turned off. If the output again rises above 1.7V, the
protection process is repeated. This offers the maximum
amount of protection against a shorted high-side
MOSFET while preventing output ringing below ground.
The 1.7V OV is not reset with VR_ON, but requires that
VDD be lowered to reset. The 1.7V OV detector is active
at all times that the controller is enabled including after
one of the other faults occurs so that the processor is
protected against high-side MOSFET leakage while the
MOSFETs are commanded off.
The ISL6266A has a thermal throttling feature. If the voltage
on the NTC pin goes below the 1.2V over-temperature
threshold, the VR_TT# pin is pulled low indicating the need
for thermal throttling to the system oversight processor. No
other action is taken within the ISL6266A in response to
NTC pin voltage.
Power Monitor
The power monitor signal is an analog output. Its magnitude
is proportional to the product of V_CCSENSE and the voltage
difference between V_droop and V_O, which is the
programmed voltage droop value, equal to load current
multiplied by the load line impedance (for example 2.1m).
The output voltage of the PMON pin in two-phase design is
given by Equation 1:
V_PMON = V_CCSENSE  V_DROOP – V_O  17.5
(EQ. 1)
Equation 1 can be expressed in terms of load current as
seen in Equation 2:
V_PMON = V_CCSENSE  I_CORE  2.1m  17.5
(EQ. 2)
The power consumed by the CPU can be calculated by
Equation 3:
P_CPU = V_PMON  17.5  0.0021   WATT
(EQ. 3)
where 0.0021 is the typical load line slope. The power
monitor load regulation is approximately 7. Within its
sourcing/sinking current capability range, when the power
monitor loading changes to 1mA, the output of the power
monitor will change to 7mV. The 7 impedance is
associated with the layout and package resistance of PMON
inside the IC. In practical applications, compared to the load
resistance on the PMON pin, 7 output impedance
contributes no significant error.
ISL6266 Features
The ISL6266 incorporates all the features previously listed
for the ISL6266A. However, the sleep state logic is slightly
altered (see Table 2). In addition to those differences, the
ISL6266 has been optimized to work with coupled-inductor
solutions. Due to mutual magnetic fields between the
individual phase windings of the coupled-inductor, the
effective per-phase inductance equals the leakage
inductance of the transformer. This can be very low (e.g.
90nH), which allows for faster channel current slew rates
and, consequently, an all-ceramic output capacitor bank can
be utilized. Additionally, the current ripple is lower than would
be produced with two discrete inductors of equivalent value
to the coupled-inductor leakage. This improves
coupled-inductor efficiency over discrete inductor solutions
for the same transient response.
In single phase operation, the active channel inductor will
continue to build a mutual field in the inactive channel inductor.
This field must be dissipated every cycle to maintain inductor
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FN6398.4
August 25, 2015