ISL6266 Datasheet, PDF (18/31 Pages) Intersil Corporation – Precision Two/One-phase CORE Voltage Regulator

ISL6266, ISL6266A
Theory of Operation
The ISL6266A is a two-phase regulator implementing Intel®
IMVP-6 protocol and includes embedded gate drivers for
reduced system cost and board area. The regulator provides
optimum steady-state and transient performance for
microprocessor core applications up to 50A. System
efficiency is enhanced by idling one phase at low-current
and implementing automatic DCM-mode operation.
The heart of the ISL6266A is R³ Technology™, Intersil’s
Robust Ripple Regulator modulator. The R³ modulator
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. The ISL6266A modulator internally
synthesizes an analog of the inductor ripple current and
uses hysteretic comparators on those signals to establish
PWM pulse widths. Operating on these large-amplitude,
noise-free synthesized signals allows the ISL6266A to
achieve lower output ripple and lower phase jitter than either
conventional hysteretic or fixed frequency PWM controllers.
Unlike conventional hysteretic converters, the ISL6266A has
an error amplifier that allows the controller to maintain a
0.5% voltage regulation accuracy throughout the VID range
from 0.75V to 1.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients results in
increased switching frequency, which gives the R³ regulator
a faster response than conventional fixed frequency PWM
controllers. Transient load current is inherently shared
between active phases due to the use of a common
hysteretic window voltage. Individual average phase
voltages are monitored and controlled to equally share the
static current among the active phases.
Start-Up Timing
With the controller's VDD voltage above the POR threshold,
the start-up sequence begins when VR_ON exceeds the
3.3V logic HIGH threshold. Approximately 100µs later, SOFT
and VOUT begin ramping to the boot voltage of 1.2V. At
start-up, the regulator always operates in a 2-phase CCM
mode regardless of control signal assertion levels. During
this interval, the SOFT capacitor is charged by 41µA current
source. If the SOFT capacitor is selected to be 20nF, the
SOFT ramp will be at 2mV/µs for a soft-start time of 600µs.
Once VOUT is within 10% of the boot voltage for 13 PWM
cycles (43µs for frequency = 300kHz), then CLK_EN# is
pulled LOW and the SOFT capacitor is charged/discharged
by approximately 200µA. Therefore, VOUT slews at
10mV/µs to the voltage set by the VID pins. Approximately
7ms later, PGOOD is asserted HIGH. Typical start-up timing
is shown in Figure 34.
V_DD
VR_ON
100µs
SOFT AND VO
10mV/µs
2.8mV/µs
VBOOT
90%
VID COMMANDED
VOLTAGE
CLK_EN#
13 SWITCHING CYCLES
IMVP-6 PGOOD
~7ms
FIGURE 34. SOFT-START WAVEFORMS USING A 15nF SOFT
CAPACITOR
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs shown in Table 1. The
entire VID table is presented in the intel IMVP-6
specification. The ISL6266A will control the no-load output
voltage to an accuracy of ±0.5% over the range of 0.75V to
1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6+
SPECIFICATION
VOUT
VID6 VID5 VID4 VID3 VID2 VID1 VID0
(V)
0
0
0
0
0
0
0 1.5000
0
0
0
0
0
0
1 1.4875
0
0
0
0
1
0
1 1.4375
0
0
1
0
0
0
1 1.2875
0
0
1
1
1
0
0 1.15
0
1
1
0
1
0
1 0.8375
0
1
1
1
0
1
1 0.7625
1
1
0
0
0
0
0 0.3000
1
1
1
1
1
1
1 0.0000
A fully-differential amplifier implements core voltage sensing
for precise voltage control at the microprocessor die. The
inputs to the amplifier are the VSEN and RTN pins.
As the load current increases from zero, the output voltage
will droop from the VID table value by an amount
proportional to current to achieve the IMVP-6+ load line. The
ISL6266A provides options for current to be measured using
either resistors in series with the channel inductors as shown
in the application circuit of Figure 33, or using the intrinsic
series resistance of the inductors as shown in the application
circuit of Figure 32. In both cases, signals representing the
inductor currents are summed at VSUM, which is the
non-inverting input to the DROOP amplifier shown in the
block diagram of Figure 1. The voltage at the DROOP pin
18
FN6398.4
August 25, 2015