ISL6266 Datasheet, PDF (19/31 Pages) Intersil Corporation – Precision Two/One-phase CORE Voltage Regulator

ISL6266, ISL6266A
minus the output voltage, VO´, is a high-bandwidth analog of
the total inductor current. This voltage is used as an input to
a differential amplifier to achieve the IMVP-6+ load line, and
also as the input to the overcurrent protection circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus maintaining the
load-line accuracy.
In addition to monitoring the total current (used for DROOP
and overcurrent protection), the individual channel average
currents are also monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to
cause the voltages presented at the ISEN pins to be equal.
The ISL6266A controller can be configured for two-channel
operation, with the channels operating 180° apart. The
channel PWM frequency is determined by the value of
R_FSET connected to pin VW as shown in Figures 32 and 33.
Input and output ripple frequencies will be the channel PWM
frequency multiplied by the number of active channels.
High Efficiency Operation Mode
The ISL6266A has several operating modes to optimize
efficiency. The controller's operational modes are designed
to work in conjunction with the Intel IMVP-6+ control signals
to maintain the optimal system configuration for all IMVP-6+
conditions. These operating modes are established by the
IMVP-6+ control signal inputs PSI#, DPRSLPVR, and
DPRSTP# as shown in Table 2. At high current levels, the
system will operate with both phases fully active, responding
rapidly to transients and delivering maximum power to the
load. At reduced load-current levels, one of the phases may
be idled. This configuration will minimize switching losses,
while still maintaining transient response capability. At the
lowest current levels, the controller automatically configures
the system to operate in single-phase automatic-DCM
mode, thus achieving the highest possible efficiency. In this
mode of operation, the lower MOSFET will be configured to
automatically detect and prevent discharge current flowing
from the output capacitor through the inductors, and the
switching frequency will be proportionately reduced, thus
greatly reducing both conduction and switching losses.
Smooth mode transitions are facilitated by the R³
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms that maintain
voltage-regulation for all control signal input sequences and
durations.
While the ISL6266A will respond according to the logic
states shown in Table 2, it can deviate from the commanded
state during sleep state exit. If the core voltage is directed by
the CPU to make a VID change that causes excessive
output capacitor inrush current when going from 1-phase
DCM to 1-phase CCM, the controller will automatically add
Phase 2 until the VID transition is complete. This is
beneficial for designs that have very large C_OUT values.
The controller contains internal counters that prevent
spurious control signal glitches from resulting in unwanted
mode transitions. Control signals of less than two switching
periods do not result in phase-idling.
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6266 AND ISL6266A
DPRSLPVR DPRSTP#
PSI#
ISL6266
ISL6266A
VID SLEW RATE
CPU MODE
0
0
0
1-phase CCM
1-phase diode emulation
fast
awake
0
0
1
2-phase CCM
2-phase CCM
fast
awake
0
1
0
1-phase CCM
1-phase diode emulation
fast
awake
0
1
1
2-phase CCM
2-phase CCM
fast
awake
1
0
0
1-phase diode emulation 1-phase diode emulation
slow (Note 5)
sleep
1
0
1
1-phase diode emulation 1-phase diode emulation
slow (Note 5)
sleep
1
1
0
1-phase CCM
1-phase diode emulation
slow
awake
1
1
1
2-phase CCM
2-phase CCM
slow
awake
NOTE:
5. The negative VID slew rate when DPRSTP# = 0 and DPRSLPVR = 1 is limited to no faster than the slow slew rate. However, slower slew rates
can be seen. To conserve power, the ISL6266A will tri-state UGATE and LGATE and let the load gradually pull the core voltage back into
regulation.
19
FN6398.4
August 25, 2015