SI596 Datasheet, PDF (2/12 Pages) Silicon Laboratories – Pb-free/RoHS-compliant

Si596
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition
Min
Typ
Max
Supply Voltage¹
V_DD
3.3 V option
2.5 V option
2.97
3.3
3.63
2.25
2.5
2.75
1.8 V option
1.71
1.8
1.89
Supply Current
I_DD
LVPECL
CML
LVDS
CMOS
—
120
135
—
110
120
—
100
110
—
90
100
Frequency Select (FS)²
V_IH
0.75 x V_DD
—
—
V_IL
—
—
0.5
Operating Temperature Range
T_A
–40
—
85
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 7 for further details.
2. FS pin includes an internal 17 k pullup resistor to V_DD. When the FS is left floating, the pullup causes
FS = 1 = second frequency selected.
Units
V
mA
V
°C
Table 2. V_C Control Voltage Input
Parameter
Symbol Test Condition
Min
Typ
Max Units
Control Voltage Tuning Slope^1,2,3
K_V
10 to 90% of V_DD
—
45
—
ppm/V
95
125
185
380
Control Voltage Linearity⁴
L_VC
BSL
–5
±1
+5
%
Incremental
–10
±5
+10
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
V_C Input Impedance
Z_VC
500
—
—
k
V_C Input Capacitance
C_VC
—
50
—
pF
Nominal Control Voltage
V_CNOM
@ f_O
—
V_DD/2
—
V
Control Voltage Tuning Range
V_C
0
V_DD
V
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 7.
2. For best jitter and phase noise performance, always choose the smallest K_V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.
3. K_V variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with V_C ranging from 10 to 90% of V_DD. Incremental slope
determined with V_C ranging from 10 to 90% of V_DD.
2
Rev. 1.0