SI5325 Datasheet, PDF (2/14 Pages) Silicon Laboratories – UP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5325
Table 1. Performance Specifications
(V_DD = 1.8, 2.5, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Temperature Range
T_A
Supply Voltage
V_DD
–40
25
85
ºC
2.97
3.3
3.63
V
2.25
2.5
2.75
V
1.62
1.8
1.98
V
Supply Current
I_DD
f_OUT = 622.08 MHz
—
Both CKOUTs enabled
LVPECL format output
251
279
mA
CKOUT2 disabled
—
217
243
mA
f_OUT = 19.44 MHz
—
Both CKOUTs enabled
CMOS format output
204
234
mA
CKOUT2 disabled
—
194
220
mA
Tristate/Sleep Mode
—
TBD
TBD
mA
Input Clock Frequency
(CKIN1, CKIN2)
CK_F
Input frequency and clock
10
multiplication ratio deter-
—
710 MHz
Output Clock Frequency
(CKOUT1, CKOUT2)
CK_OF
mined by programming
device PLL dividers. Consult
10
970
—
945 MHz
—
1134
Silicon Laboratories configu-
ration software DSPLLsim at
1213
—
1417
www.silabs.com/timing to
determine PLL divider set-
tings for a given input fre-
quency/clock multiplication
ratio combination.
Input Clocks (CKIN1, CKIN2)
Differential Voltage Swing CKN_DPP
Common Mode Voltage CKN_VCM
1.8 V ±10%
2.5 V ±10%
0.25
—
0.9
—
1.0
—
1.9
V_PP
1.4
V
1.7
V
3.3 V ±10%
1.1
—
1.95
V
Rise/Fall Time
Duty Cycle
CKN_TRF
CKN_DC
20–80%
Whichever is less
—
11
ns
40
—
60
%
50
—
—
ns
Output Clocks (CKOUT1, CKOUT2)
Common Mode
Differential Output Swing
Single Ended Output
Swing
V_OCM
V_OD
V_SE
LVPECL
100 Ω load
line-to-line
V_DD – 1.42
—
V_DD – 1.25 V
1.1
—
1.9
V
0.5
—
0.93
V
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2
Preliminary Rev. 0.26