SI5325 Datasheet, PDF (13/14 Pages) Silicon Laboratories – UP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

DOCUMENT CHANGE LIST
Revision 0.23 to Revision 0.24
Clarified that the two outputs have a common, higher
frequency source on page 1.
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 3.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Updated “2. Pin Descriptions: Si5325”.
Removed references to latency control, INC, and DEC.
Changed font for register names to underlined italics.
Updated "3. Ordering Guide" on page 9.
Added “5. Recommended PCB Layout”.
Revision 0.24 to Revision 0.25
Updated Section "2. Pin Descriptions: Si5325" on
page 6.
Revision 0.25 to Revision 0.26
Removed Figure 1. “Typical Phase Noise Plot.”
Changed pins 11 and 15 from NC to VDD in “2. Pin
Descriptions: Si5325”.
Si5325
Preliminary Rev. 0.26
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