SI5325 Datasheet, PDF (10/14 Pages) Silicon Laboratories – UP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5325
4. Package Outline: 36-Pin QFN
Figure 3 illustrates the package details for the Si5325. Table 4 lists the values for the dimensions shown in the
illustration.
Figure 3. 36-Pin Quad Flat No-lead (QFN)
Table 4. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
Min
Nom
Max
A
0.80
0.85
0.90
L
0.50
0.60
0.75
A1
0.00
0.01
0.05
θ
—
—
12º
b
0.18
0.23
0.30
aaa
—
—
0.10
D
6.00 BSC
bbb
—
—
0.10
D2
3.95
4.10
4.25
ccc
—
—
0.05
e
0.50 BSC
ddd
—
—
0.10
E
6.00 BSC
eee
—
—
0.05
E2
3.95
4.10
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
10
Preliminary Rev. 0.26