SI53159-EVB Datasheet, PDF (2/6 Pages) Silicon Laboratories – Power consumption test

Si53159-EVB
1. Front Panel
Differential Buffer Input
for on Si53159-EVB only
Power Connectors
DIFF8 Differential output
DIFF7 Differential output
CKPWRGD/ Power down input
control
I2C connect -For I2C read and
write. In sequence SData, Gnd,
SCLK from left to right.
OE0 and OE1 hardware
input control for DIFF0
and DIFF1 respectively
tt
GND Connector
3.3V Power Supply Connector
OE2, OE3, OE4/5 and
OE6/8 hardware inputs
control for DIFF2, DIFF3,
DIFF4 though DIFF5 and
DIFF6 through DIFF8
outputs respectively
DIFF0 Differential output
Si53159 device mount
DIFF6 Differential output
DIFF5 Differential output
Figure 1. Evaluation Module Front Panel
DIFF4 Differential output
DIFF1 Differential output
DIFF3 Differential output
DIFF2 Differential output
Jumper Label
OE0
OE1
OE2
OE3
OE4/5
OE6/8
CLKPWGD/PD
SDATA
SCLK
Table 1. Input Jumper Settings
Type
Description
I _{OE0, 3.3 V Input for Enabling DIFF0 Clock Output.}
1 = DIFF0 enabled, 0 = DIFF0 disabled.
I _{OE1, 3.3 V Input for Enabling DIFF1 Clock Output.}
1 = DIFF1 enabled, 0 = DIFF1 disabled.
I _{OE2, 3.3 V Input for Enabling DIFF2 Clock Output.}
1 = DIFF2 enabled, 0 = DIFF2 disabled.
I _{OE3, 3.3 V Input for Enabling DIFF3 Clock Output.}
1 = DIFF3 enabled, 0 = DIFF3 disabled.
I _{OE4/5, 3.3 V Input for Enabling DIFF4 and DIFF5 Clock Outputs.}
1 = DIFF4 & DIFF5 enabled, 0 = DIFF4 & DIFF5 disabled.
I _{OE6/8, 3.3 V Input for Enabling DIFF6, DIFF7 and DIFF8 Clock Outputs.}
1 = DIFF6, DIFF7 & DIFF8 enabled, 0 = DIFF6, DIFF7 & DIFF8 disabled.
I 3.3 V LVTTL Input.
After CLKPWGD (active high) assertion, this pin becomes a real-time input for
asserting power down (active low).
I/O _{SMBus-Compatible SDATA.}
I SMBus-Compatible SCLOCK.
2
Rev. 0.1