SI53159-EVB Datasheet, PDF (1/6 Pages) Silicon Laboratories – Power consumption test

Si53159-EVB
Si53159 EVALUATION BOARD USER’S GUIDE
Description
EVB Features
The Si53159 is a nine port PCIe clock buffer compliant
to the PCIe Gen1, Gen2 and Gen3 standards. The
Si53159 is a 48-pin QFN device that operates on a
3.3 V power supply and can be controlled using SMBus
signals along with hardware control input pins. The
device is spread aware and accepts frequency spread
differential clock frequency range from 100 to 210 MHz.
The connections are described in this document.
This document is intended to be used in conjunction
with the Si53159 device and data sheet for the following
tests:
 PCIe Gen1, Gen2, Gen3 compliancy
 Power consumption test
 Jitter performance
 Testing out I²C code for signal tuning
 In-system validation where SMA connectors are
present
Power connectors
VDD = 3.3 V
power supply
GND
CKPWRGD/Power down enable
Differential
Clock Input
DIFF8 connection DIFF7 connection
for application
for application
SDATA
SCLK
GND
DIFF0 Output Enable
DIFF1 Output Enable
DIFF2 Output Enable
DIFF3 Output Enable
DIFF4/DIFF5 Output Enable
DIFF6/DIFF8 Output Enable
DIFF0 connection
for application
Si53159
DIFF6
connection
for
application
DIFF5
connection
for
application
DIFF4
connection
for
application
Rev. 0.1 1/12
DIFF1 connection for
application
DIFF2 connection DIFF3 connection
for application
for application
Copyright © 2012 by Silicon Labs
Si53159-EVB