ISL6730 Datasheet, PDF (2/19 Pages) Intersil Corporation – Reduce component size requirements

ISL6730A, ISL6730B, ISL6730C, ISL6730D
Pin Configuration
ISL6730A, ISL6730B, ISL6730C, ISL6730D
(10 LD MSOP)
TOP VIEW
GND 1
ISEN 2
ICOMP 3
VIN 4
BO 5
10 GATE
9 VCC
8 VREG
7 FB
6 COMP
Pin Descriptions
PIN # I/O SYMBOL
DESCRIPTION
1 - GND Ground pin. All voltage levels refer to this pin.
2 I ISEN Current sense pin. The current through this pin is proportional to the inductor current.
3 I/O ICOMP Current error amplifier output pin.
4I
VIN Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider from
the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the input current.
The phase lag is required to compensate the phase lead generated by the EMI filter.
5 I/O BO This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will follow
the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor R_IS. The decoupling capacitor provides ripple
filtering. When the voltage at the BO pin (V_BO) drops below brownout voltage threshold, the controller enters shutdown mode
and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling threshold.
6 I/O COMP Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will slowly
ramp up the voltage of the COMP pin.
7I
FB Voltage feed back pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage. When
the FB pin voltage exceeds 104% of the reference voltage, overvoltage-protection is triggered and gate drive is disabled. When
the FB pin is below 10%, the device is put into shutdown mode. There is an internal pull-down current source for open loop
protection.
8 - VREG Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND with
a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.
9 I VCC Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.
10 O GATE Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and 1.5A
source capability.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6730AFUZ
6730A
-40 to +125
10 Ld MSOP
M10.118
ISL6730BFUZ
6730B
-40 to +125
10 Ld MSOP
M10.118
ISL6730CFUZ
6730C
-40 to +125
10 Ld MSOP
M10.118
ISL6730DFUZ
6730D
-40 to +125
10 Ld MSOP
M10.118
ISL6730AEVAL1Z
Evaluation Board
ISL6730BEVAL1Z
Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page. For more information on MSL please see techbrief TB363.
2
FN8258.1
August 8, 2013