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SI5330A-A00200-GM Datasheet, PDF (19/20 Pages) Silicon Laboratories – 1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR | |||
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DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
ï® Clarified documentation to reflect that Pin 19 is OEB
(OE Enable Low).
ï® Updated Table 4, âJitter Specificationsâ on page 7.
Revision 0.2 to Revision 0.3
ï® Major editorial updates to improve clarity.
ï® Updated âAdditive Jitterâ Specification Table.
ï® Updated âCore Supply Currentâ Specification in
Table 2.
ï® Removed the Low-Power LVPECL output options
from the ordering table in section 6.
ï® Removed D/E ordering options.
Revision 0.3 to Revision 0.35
ï® Typo of 150 ps on front page changed to 150 fs.
ï® Updated PCB layout notes.
ï® Added no ac coupling for LVDS outputs.
ï® Changed input rise/fall time spec to 2 ns.
Revision 0.35 to Revision 1.0
ï® Added maximum junction temperature specification
to Table 9 on page 8.
ï® Added minimum and maximum duty cycle
specifications to Table 4 on page 5.
ï® Updated Table 3, âPerformance Characteristics,â on
page 5.
ï¬ï Added maximum propagation delay spec (4 ns).
ï¬ï Added test condition to tLOS_B in Table 3 on page 5.
ï¬ï Removed reference to frequency in Output-Output
Skew.
ï® Updated Table 4, âInput and Output Clock
Characteristics,â on page 5.
ï¬ï Input voltage (max) changed â3.63â to âVDDâ
ï¬ï Input voltage swing (max) change â3.63â with âââ.
ï® Added Table 6, âOutput Control Pins (LOS),â on
page 7.
ï® Added tape and reel ordering information to "6.
Orderable Part Numbers and Device Functionality"
on page 14.
ï® Added "9. Top Marking" on page 18.
Rev. 1.0
Si5330
19
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