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SI5330A-A00200-GM Datasheet, PDF (1/20 Pages) Silicon Laboratories – 1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR | |||
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Si5330
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW
CLOCK BUFFER/LEVEL TRANSLATOR
Features
ï® Supports single-ended or
differential input clock signals
ï® Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
ï® Provides signal level translation
ï¬ï Differential to single-ended
ï¬ï Single-ended to differential
ï¬ï Differential to differential
ï¬ï Single-ended to single-ended
ï® Wide frequency range
ï¬ï LVPECL, LVDS: 5 to 710 MHz
ï¬ï HCSL: 5 to 250 MHz
ï¬ï SSTL, HSTL: 5 to 350 MHz
ï¬ï CMOS: 5 to 200 MHz
ï® Additive jitter: 150 fs RMS typ
ï® Output-output skew: 100 ps
ï® Propagation delay: 2.5 ns typ
ï® Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
ï® Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
ï® Loss of Signal (LOS) indicator
allows system clock monitoring
ï® Output Enable (OEB) pin allows
glitchless control of output clocks
ï® Low power: 10 mA typical core
current
ï® Industrial temperature range:
â40 to +85 °C
ï® Small size: 24-lead, 4 x 4 mm
QFN
Applications
ï® High Speed Clock Distribution
ï® Ethernet Switch/Router
ï® SONET / SDH
ï® PCI Express 2.0/3.0
ï® Fibre Channel
ï® MSAN/DSLAM/PON
ï® Telecom Line Cards
Ordering Information:
See page 14.
Pin Assignments
IN1
IN2
IN3
RSVD_GND
RSVD_GND
RSVD_GND
24 23 22 21 20 19
GND
GND
7 8 9 10 11 12
CLK1A
CLK1B
VDDO1
VDDO2
CLK2A
CLK2B
Functional Block Diagram
VDD
Si5330
VDDO0
CLK0
Single-ended
IN
or
Differential
VDDO1
CLK1
VDDO2
CLK2
Single-ended
or
Differential
LOS
OEB
Control
VDDO3
CLK3
Rev. 1.0 4/12
Copyright © 2012 by Silicon Laboratories
Si5330
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