SI52147 Datasheet, PDF (19/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR

Si52147
Pin #
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Table 7. Part Number 48-Pin QFN Descriptions
Name
VDD
DIFF8
DIFF8
SCLK
SDATA
CKPWRGD_PDB
VDD_CORE
XOUT
XIN/CLKIN
NC
NC
VSS_CORE
VSS
NC
NC
Type
PWR 3.3 V Power Supply
Description
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
I SMBus compatible SCLOCK
I/O SMBus compatible SDATA
I, PU
PWR
3.3 V CMOS input. A real-time active low input for asserting power
down (PDB) and disabling all outputs (internal 100 k pull-up).
3.3 V Power Supply
O 25.00 MHz Crystal output, Float XOUT if using only CLKIN (Clock input)
I 25.00 MHz Crystal input or 3.3 V, 25 MHz Clock Input
NC No Connect
NC No Connect
GND Ground
GND Ground
NC No Connect
NC No Connect
GND
GND Ground for bottom pad of the IC.
Preliminary Rev. 0.1
19