SI52147 Datasheet, PDF (17/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR

5. Pin Descriptions: 48-Pin QFN
Si52147
48 47 46 45 44 43 42 41 40 39 38 37
VDD 1
36 DIFF8
VDD 2
35 DIFF8
OE0¹ 3
34 _VDD
OE1¹ 4
SSON² 5
VSS_PLL3 6
VSS_PLL4 7
OE2¹ 8
OE3¹ 9
OE[4:5]¹ 10
OE[6:8]^{1 11}
VDD 12
49
GND
33 DIFF7
32 DIFF7
31 DIFF6
30 DIFF6
29 _VDD
28 _DIFF5
27 DIFF5
26 DIFF4
25 DIFF4
13 14 15 16 17 18 19 20 21 22 23 24
Pin #
1
2
3
4
5
6
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Name
VDD
VDD
OE0
OE1
SSON
VSS
Table 7. Part Number 48-Pin QFN Descriptions
Type
PWR 3.3 V Power Supply
Description
PWR 3.3 V Power Supply
I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I, PD 3.3 V-tolerant input for enabling –0.5% spread on DIFF clocks (internal
100 k pull-down)
GND Ground
Preliminary Rev. 0.1
17