SI52147 Datasheet, PDF (18/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR

Si52147
Pin #
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Name
VSS
OE2
OE3
OE[4:5]
OE[6:8]
VDD
VDD
DIFF0
DIFF0
VSS
DIFF1
DIFF1
DIFF2
DIFF2
DIFF3
DIFF3
VDD
VSS
DIFF4
DIFF4
DIFF5
DIFF5
VSS
DIFF6
DIFF6
DIFF7
DIFF7
Table 7. Part Number 48-Pin QFN Descriptions
Type
GND Ground
Description
I,PU 3.3 V input to disable DIFF2 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF3 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU _{3.3 V input to disable DIFF[4:5] (internal 100 k pull-up).}
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF[6:8] (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
PWR 3.3 V Power Supply
PWR 3.3 V Power Supply
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
VSS Ground
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3V Power Supply
GND Ground
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
GND Ground
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
18
Preliminary Rev. 0.1