CP2105 Datasheet, PDF (19/24 Pages) Silicon Laboratories – Data format: 8 data bits, 1 stop bit Parity: Even, Pdd, No parity Baud rates: 2400 bps to 921600 bps

CP2105
Alternatively, if 3.0 to 3.6 V power is supplied to the V_DD pin, the CP2105 can function as a USB self-powered
device with the voltage regulator bypassed. For this configuration, the REGIN input should be tied to V_DD to bypass
the voltage regulator. A typical connection diagram showing the device in a self-powered application with the
regulator bypassed is shown in Figure 9.
The USB max power and power attributes descriptor must match the device power usage and configuration. See
application note “AN144: CP21xx Customization Guide” for information on how to customize USB descriptors for
the CP2105.
VIO ^{Note 2}
3.3 V
Power
Note 3
VIO
VDD
REGIN
1-5 F
0.1 F
CP2105
RST
SUSPEND / RI_ECI
NC / DCD_ECI / VPP
GPIO0_ECI / DTR_ECI
GPIO.1_ECI / DSR_ECI
RTS_ECI
CTS_ECI
RXD_ECI
TXD_ECI
4.7 k
Note 4
Enhanced
UART
and GPIO
Signals
USB
Connector
VBUS
D+
D-
GND
GND
VBUS
D+
D-
Note 1
RXD_SCI
TXD_SCI
RTS_SCI
CTS_SCI
SUSPEND / RI_SCI
GPIO.0_SCI / DCD_SCI
GPIO.1_SCI / DTR_SCI
GPIO.2_SCI / DSR_SCI
Standard
UART
and GPIO
Signals
Note 1 : Avalanche transient voltage suppression diodes compatible with Full-speed USB should be
added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.
Note 2 : An external pull-up is not required, but can be added for noise immunity.
Note 3 : VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface
voltage.
Note 4 : If configuration ROM is to be programmed via USB, a 4.7 F capacitor must be added
between NC / DCD_ECI / VPP and ground. During a programming operation, the pin should
not be connected to other circuitry, and VDD must be at least 3.3 V.
Figure 9. Typical Self-Powered Connection Diagram (Regulator Bypass)
Rev. 1.0
19