SI1000-E-GM2 Datasheet, PDF (18/382 Pages) Silicon Laboratories – MCU with Integrated 240–960 MHz EZRadioPRO® Transceiver

Si1000/1/2/3/4/5
C2CK/RST
VDD
GND
XTAL3
XTAL4
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
C2D
VREG
CIP-51 8051
Controller Core
64k Byte ISP Flash
Program Memory
256 Byte SRAM
4096 Byte XRAM
CRC
Engine
SYSCLK
P0.2/XTAL1
P0.3/XTAL2
Precision
24.5 MHz
Oscillator
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
SFR
Bus
SmaRTClock
Oscillator
System Clock
Configuration
Analog Peripherals
6-bit
IREF
IREF0
Internal External
VREF VREF
10-bit
300ksps
ADC
A
M
U
X
VDD
VREF
Temp
Sensor
GND
CP0, CP0A +
CP1, CP1A + ^-
-
Comparators
Digital Peripherals
Transceiver Control Interface
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
SPI 0
Priority
Crossbar
Decoder
RF XCVR
(240-960 MHz,
+20 dBm)
PA
AGC
LNA
Mixer
PGA
ADC
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
OSC
TX
RXp
RXn
XIN
XOUT
Port I/O ²²
Config
ANALOG &
DIGITAL I/O
Figure 1.1. Si1000 Block Diagram
C2CK/RST
VDD
GND
XTAL3
XTAL4
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
C2D
VREG
CIP-51 8051
Controller Core
32k Byte ISP Flash
Program Memory
256 Byte SRAM
4096 Byte XRAM
CRC
Engine
SYSCLK
P0.2/XTAL1
P0.3/XTAL2
Precision
24.5 MHz
Oscillator
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
SFR
Bus
SmaRTClock
Oscillator
System Clock
Configuration
Analog Peripherals
6-bit
IREF
IREF0
Internal External
VREF VREF
10-bit
300ksps
ADC
A
M
U
X
VDD
VREF
Temp
Sensor
GND
CP0, CP0A +
CP1, CP1A + ^-
-
Comparators
Digital Peripherals
Transceiver Control Interface
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
SPI 0
Priority
Crossbar
Decoder
RF XCVR
(240-960 MHz,
+20 dBm)
PA
AGC
LNA
Mixer
PGA
ADC
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
OSC
TX
RXp
RXn
XIN
XOUT
Port I/O ²²
Config
ANALOG &
DIGITAL I/O
Figure 1.2. Si1001 Block Diagram
18
Rev. 1.3