EM34X-VREVK Datasheet, PDF (161/237 Pages) Silicon Laboratories – High-Performance, Integrated RF4CE System-on-Chip

EM341
Register 9.10. TIMx_ARR
TIM1_ARR: Timer 1 Auto-Reload Register
TIM2_ARR: Timer 2 Auto-Reload Register
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
TIM_ARR
Bit
7
6
5
4
3
2
1
0
Name
TIM_ARR
TIM1_ARR: Address: 0x4000E02C Reset: 0xFFFF
TIM2_ARR: Address: 0x4000F02C Reset: 0xFFFF
Bitname
TIM_ARR
Bitfield
[15:0]
Access
RW
Description
TIM_ARR is the value to be loaded in the shadow auto-reload register.
The auto-reload register is buffered. Writing or reading the auto-reload reg-
ister accesses the buffer register. The content of the buffer register is trans-
fered in the shadow register permanently or at each UEV, depending on the
auto-reload buffer enable bit (TIM_ARBE) in TMRx_CR1 register. The UEV
is sent when the counter reaches the overflow point (or underflow point
when down-counting) and if the TIM_UDIS bit equals 0 in the TMRx_CR1
register. It can also be generated by software. The counter is blocked while
the auto-reload value is 0.
162
Rev 1.0