EM34X-VREVK Datasheet, PDF (111/237 Pages) Silicon Laboratories – High-Performance, Integrated RF4CE System-on-Chip

EM341
Register 8.32. SCx_RXERRB
SC1_RXERRB: DMA First Receive Error Register B
SC2_RXERRB: DMA First Receive Error Register B
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
0
0
SC_RXERRB
Bit
7
6
5
4
3
2
1
0
Name
SC_RXERRB
SC1_RXERRB: Address: 0x4000C838 Reset: 0x0
SC2_RXERRB: Address: 0x4000C038 Reset: 0x0
Bitname
SC_RXERRB
Bitfield
[13:0]
Access
Description
R The offset from the start of DMA receive buffer B of the first byte received
with a parity, frame, or overflow error. Note that an overflow error occurs at
the input to the receive FIFO, so this offset is 4 bytes before the overflow
position. If there is no error, it reads zero. This register will not be updated
by subsequent errors until the buffer unloads and is reloaded, or the receive
DMA is reset.
112
Rev 1.0