EFR32FG12 Datasheet, PDF (150/183 Pages) –

EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
6.8 Alternate Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO
pin. Refer to 6.7 GPIO Functionality Table for a list of functions available on each GPIO pin.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.8. Alternate Functionality Overview
Alternate
Functionality
ACMP0_O
ACMP1_O
ADC0_EXTN
ADC0_EXTP
BOOT_RX
0-3
0: PA0
1: PA1
2: PA2
3: PA3
0: PA0
1: PA1
2: PA2
3: PA3
0: PA0
0: PA1
0: PF1
4-7
4: PA4
5: PA5
6: PB11
7: PB12
4: PA4
5: PA5
6: PB11
7: PB12
LOCATION
8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31
Description
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP0, digital out-
put.
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP1, digital out-
put.
Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin.
Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin.
Bootloader RX.
BOOT_TX
0: PF0
Bootloader TX.
CMU_CLK0
CMU_CLK1
CMU_CLKI0
0: PA1
1: PB15
2: PC6
3: PC11
0: PA0
1: PB14
2: PC7
3: PC10
0: PB13
1: PF7
2: PC6
3: PB6
4: PD9
5: PD14
6: PF2
7: PF7
4: PD10
5: PD15
6: PF3
7: PF6
4: PA5
Clock Management
Unit, clock output
number 0.
Clock Management
Unit, clock output
number 1.
Clock Management
Unit, clock output
number I0.
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