EFM32G800 Datasheet, PDF (13/22 Pages) Silicon Laboratories – Memory Protection Unit

3.3 GPIO Pinout Overview
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The specific GPIO pins available in EFM32G800 is shown in Table 3.3 (p. 13) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 3.3. GPIO Pinout
Port
Port A
Port B
Port C
Port D
Port E
Port F
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
-
-
-
-
-
-
PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
3.4 Bonding Instructions
All pads should be bonded out, with the exception of the pads labeled “NC” and listed as “Do not connect”
in Table 3.1 (p. 5) . Gold bond wires are recommended for these devices.
Both voltage regulator output decouple pads (DEC_0, DEC_1) must be bonded out and electrically
connected on the PCB. In the packaged devices, both of these pads are bonded to a single DECOUPLE
pin.
3.5 Wafer Description
Table 3.4. Wafer and Die Information
Parameter
Value
Device Family
EFM32G (Gecko)
Wafer Diameter
8 in
Die Dimensions (Outer edge of seal ring)
3380 µm × 3250 µm
Wafer Thickness (No backgrind)
725 µm ±15 µm
(28.54 mil ±1 mil)
Wafer Identification
Notch
Scribe Street Width
Die Per Wafer ¹
80 µm × 80 µm
Contact sales for information
Passivation
Standard
Wafer Packaging Detail
Wafer Jar
Bond Pad Dimensions
65 µm (parallel to die edge) × 66 µm
Bond Pad Pitch Minimum
81 µm
Maximum Processing Temperature
250°C
Electronic Die Map Format
.txt
1_{Note: This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer).}
2015-05-22 - EFM32G800FXX - d0322_Rev1.90
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