EM342 Datasheet, PDF (109/143 Pages) Silicon Laboratories – High-Performance, Integrated RF4CE System-on-Chip

EM342
Register 9.4. INT_PENDCLR: Top-Level Clear Interrupts Pending Register
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
INT_DEBUG
Bit
15
14
13
12
11
10
9
8
Name INT_IRQD INT_IRQC Reserved
INT_IRQA
Reserved INT_MACRX INT_MACTX INT_MACTMR
Bit
7
6
5
4
3
2
1
0
Name INT_SEC Reserved INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT Reserved
Reserved
Address: 0xE000E280 Reset: 0x0
Bitname
INT_DEBUG
INT_IRQD
INT_IRQC
INT_IRQA
INT_MACRX
INT_MACTX
INT_MACTMR
INT_SEC
INT_SC1
INT_SLEEPTMR
INT_BB
INT_MGMT
Bitfield
[16]
[15]
[14]
[12]
[10]
[9]
[8]
[7]
[5]
[4]
[3]
[2]
Access
Description
RW Write 1 to unpend debug interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend IRQD interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend IRQC interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend IRQA interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend MAC receive interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend MAC transmit interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend MAC timer interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend security interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend serial controller 1 interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend sleep timer interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend baseband interrupt. (Writing 0 has no effect.)
RW Write 1 to unpend management interrupt. (Writing 0 has no effect.)
Rev 1.0
109