S-5724CNBL1-M3T1U Datasheet, PDF (8/29 Pages) Seiko Instruments Inc – HIGH-SPEED BIPOLAR HALL EFFECT LATCH

LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5724 Series
Rev.1.2_01
 Electrical Characteristics
1. Product without power-down function
1. 1 S-5724CxBxx
Table 8
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Power supply voltage VDD
−
1.60 1.85 3.50 V
−
Current consumption IDD Average value
−
6.0 11.0 μA
1
Output voltage
Nch open-drain output Output transistor Nch,
product
IOUT = 0.5 mA
−
−
0.4
V
2
VOUT
CMOS output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Pch,
IOUT = −0.5 mA
−
−
VDD −
0.4
−
0.4
−
V
V
2
3
Leakage current
ILEAK
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
1
μA
4
Awake mode time
tAW
−
− 0.05 −
ms
−
Sleep mode time
tSL
−
− 6.00 −
ms
−
Operating cycle
tCYCLE tAW + tSL
− 6.05 12.00 ms
−
1. 2 S-5724DxBxx
Table 9
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Power supply voltage VDD
−
1.60 1.85 3.50 V
−
Current consumption IDD Average value
− 26.0 45.0 μA
1
Nch open-drain output Output transistor Nch,
product
IOUT = 0.5 mA
−
−
0.4
V
2
Output voltage
VOUT
CMOS output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Pch,
IOUT = −0.5 mA
−
−
VDD −
0.4
−
0.4
−
V
V
2
3
Leakage current
ILEAK
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
1
μA
4
Awake mode time
tAW
−
Sleep mode time
tSL
−
Operating cycle
tCYCLE tAW + tSL
− 0.05 −
ms
−
− 1.20 −
ms
−
− 1.25 2.50 ms
−
8