S-5724CNBL1-M3T1U Datasheet, PDF (11/29 Pages) Seiko Instruments Inc – HIGH-SPEED BIPOLAR HALL EFFECT LATCH

LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.1.2_01
S-5724 Series
2. 2 S-5724IxBxx
Table 12
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Power supply voltage
VDD
−
1.60 1.85 3.50 V
−
Current consumption
IDD
Average value
−
26.0 45.0 μA
1
Current consumption during
power-down
IDD2
VCE = VSS
−
−
1
μA
6
Output voltage
Nch open-drain output Output transistor Nch,
product
IOUT = 0.5 mA
−
−
0.4
V
2
VOUT
CMOS output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Pch,
IOUT = −0.5 mA
−
VDD −
0.4
−
−
0.4
−
V
V
2
3
Leakage current
ILEAK
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
1
μA
4
Awake mode time
tAW
−
−
0.05 −
ms
−
Sleep mode time
tSL
−
Operating cycle
tCYCLE tAW + tSL
Enabling pin input voltage "L" VCEL
−
−
1.20 −
ms
−
−
1.25 2.50 ms
−
−
−
VDD ×
0.3
V
−
Enabling pin input voltage "H" VCEH
−
VDD × 0
.7
−
−
V
−
Enabling pin input current "L" ICEL
Enabling pin input current "H" ICEH
VDD = 1.85 V, VCE = 0 V
VDD = 1.85 V, VCE = 1.85 V
−1
−
−1
−
1
μA
7
1
μA
8
Power-down transition time tOFF
Enable transition time
tON
−
−
−
100 μs
−
−
−
−
100 μs
−
Output logic update time after
inputting "H" to enabling pin
tOE
−
−
−
200 μs
−
11