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S-5724CNBL1-M3T1U Datasheet, PDF (12/29 Pages) Seiko Instruments Inc – HIGH-SPEED BIPOLAR HALL EFFECT LATCH | |||
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LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5724 Series
Rev.1.2_01
2. 3 S-5724JxBxx
Table 13
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Condition
Min.
Typ. Max.
Unit
Test
Circuit
Power supply voltage
VDD
â
1.60 1.85 3.50
V
â
Current consumption
IDD
Average value
â 640.0 1000.0 μA
1
Current consumption during
power-down
IDD2
VCE = VSS
â
â
1
μA
6
Output voltage
Nch open-drain output Output transistor Nch,
product
IOUT = 0.5 mA
â
â
0.4
V
2
VOUT
CMOS output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Pch,
IOUT = â0.5 mA
â
VDD â
0.4
â
â
0.4
â
V
V
2
3
Leakage current
ILEAK
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
â
â
1
μA
4
Awake mode time
tAW
â
â
50
â
μs
â
Sleep mode time
tSL
â
Operating cycle
tCYCLE tAW + tSL
Enabling pin input voltage "L" VCEL
â
â
0
â
μs
â
â
50 100 μs
â
â
â
VDD Ã
0.3
V
â
Enabling pin input voltage "H" VCEH
â
VDD Ã
0.7
â
â
V
â
Enabling pin input current "L" ICEL
Enabling pin input current "H" ICEH
VDD = 1.85 V, VCE = 0 V
VDD = 1.85 V, VCE = 1.85 V
â1
â
1
μA
7
â1
â
1
μA
8
Power-down transition time tOFF
Enable transition time
tON
â
â
â 100 μs
â
â
â
â 100 μs
â
Output logic
nputting "H"
update time afteri
to enabling pin
tOE
â
â
â 200 μs
â
12
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