S-24C08C Datasheet, PDF (26/33 Pages) Seiko Instruments Inc – Write protect function during the low power supply voltage

2-WIRE SERIAL E²PROM
S-24C08C (WLP PRODUCT)
Rev.1.0_00_H
6. Data hold time (t_HD.DAT = 0 ns)
If SCL and SDA of the S-24C08C are changed at the same time, it is necessary to prevent a start / stop condition
from being mistakenly recognized due to the effect of noise.
The S-24C08C may error if it does not recognize a start / stop condition correctly during transmission.
It is recommended to set the delay time of 0.3 μs minimum from a falling edge of SCL for the SDA.
This is to prevent S-24C08C from going in a start / stop condition due to the time lag caused by the load of the bus
line.
t_HD.DAT = 0.3 μs min.
SCL
SDA
Figure 27 S-24C08C Data Hold Time
7. SDA pin and SCL pin noise suppression time
The S-24C08C includes a built-in low-pass filter at the SDA and SCL pins to suppress noise. This means that if the
power supply voltage is 5.0 V, noise with a pulse width of 130 ns or less can be suppressed.
For details of the assurable value, refer to noise suppression time (t_l) in Table 11.
300
Noise Suppression Time (t_I) max.
200
[ns]
100
2
3
4
5
Power supply voltage (V_CC)
[V]
Figure 28 Noise Suppression Time for SDA and SCL Pins
26