S-24C08C Datasheet, PDF (22/33 Pages) Seiko Instruments Inc – Write protect function during the low power supply voltage

2-WIRE SERIAL E²PROM
S-24C08C (WLP PRODUCT)
Rev.1.0_00_H
3. Phase adjustment during S-24C08C access
The S-24C08C does not have a pin to reset (the internal circuit). The users cannot forcibly reset it externally. If the
communication to the S-24C08C interrupted, the users need to handle it as you do for software.
In the S-24C08C, users are able to reset the internal circuit by inputting a start condition and a stop condition.
Although the reset signal is input to the master device, the S-24C08C’s internal circuit does not go in reset, but it does
by inputting a stop condition to the S-24C08C. The S-24C08C keeps the same status thus cannot do the next
operation. Especially, this case corresponds to that only the master device is reset when the power supply voltage
drops.
If the power supply voltage restored in this status, input the instruction after resetting (adjusting the phase with the
master device) the S-24C08C. How to reset is shown below.
[How to reset S-24C08C]
The S-24C08C is able to be reset by a start and stop instructions. When the S-24C08C is reading data “0” or is
outputting the acknowledgment signal, outputs “0” to the SDA line. In this status, the master device cannot output
an instruction to the SDA line. In this case, terminate the acknowledgment output operation or the Read operation,
and then input a start instruction. Figure 23 shows this procedure.
First, input a start condition. Then transmit 9 clocks (dummy clock) of SCL. During this time, the master device sets
the SDA line to “H”. By this operation, the S-24C08C interrupts the acknowledgment output operation or data
output, so input a start condition^*1. When a start condition is input, the S-24C08C is reset. To make doubly sure,
input the stop condition to the S-24C08C. The normal operation is then possible.
Start
Condition
Dummy Clock
Start
Condition
Stop
Condition
SCL
1
2
8
9
SDA
Figure 23 Resetting S-24C08C
*1. After 9 clocks (dummy clock), if the SCL clock continues to being output without inputting a start condition,
S-24C08C may go in the write operation when it receives a stop condition. To prevent this, input a start
condition after 9 clocks (dummy clock).
Remark Regarding this reset procedure with dummy clock, it is recommended to perform at the system
initialization after applying the power supply voltage.
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