S-24CS64A Datasheet, PDF (25/44 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM

Rev.3.3_00
2-WIRE CMOS SERIAL E²PROM
S-24CS64A
6. Data hold time (t_{HD. DAT} = 0 ns)
If SCL and SDA of the E²PROM are changed at the same time, it is necessary to prevent the start/stop
condition from being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly
recognized during communication, the E²PROM enters the standby status.
It is recommended that SDA is delayed from the falling edge of SCL by 0.3 µs minimum in the S-24CS64A.
This is to prevent time lag caused by the load of the bus line from generating the stop (or start) condition.
SCL
t_{HD. DAT} = 0.3 µs Min.
SDA
Figure 29 E²PROM Data Hold Time
7. SDA pin and SCL pin noise suppression time
The S-24CS64A includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This means
that if the power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can be suppressed.
The guaranteed for details, refer to noise suppression time (t_I) in Table 11.
300
Noise suppression time (t_I) Max.
200
[ns]
100
2 345
Power supply voltage (V_CC)
[V]
Figure 30 Noise Suppression Time for SDA and SCL Pins
Seiko Instruments Inc.
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