S-24CS64A Datasheet, PDF (18/44 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM

2-WIRE CMOS SERIAL E²PROM
S-24CS64A
Rev.3.3_00
8. Address Increment Timing
The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the
read data in read operation and the the falling edge of the SCL clock for the 8th bit of the received data in
write operation.
SCL
SDA
8
9
1
R / W=1
ACK Output
D7 Output
8
9
D0 Output
Address Increment
Figure 18 Address Increment Timing in Reading
SCL
SDA
8
9
1
R / W=0
ACK Output D7 Input
8
9
D0 Input
ACK Output
Address Increment
Figure 19 Address Increment Timing in Writing
„ Write Inhibition Function at Low Power Voltage
The S-24CS64A have a detection circuit for low power voltage. The detection circuit cancels a write
instruction when the power voltage is low or the power switch is on. The detection voltage is 1.85 V
typically and the release voltage is 1.95 V typically, the hysteresis of approximate 0.1 V thus exists. (See
Figure 20.)
When a low power voltage is detected, a write instruction is canceled at the reception of a stop condition.
When the power voltage lowers during a data transmission or a write operation, the date at the address of
the operation is not assured.
Power supply voltage
Hysteresis width
0.1 V approximately
Detection voltage (-VDET)
1.85 V typ.
Release voltage (+VDET)
1.95 V typ.
Write Instruction
cancel
Figure 20 Operation at low power voltage
18
Seiko Instruments Inc.