S-19311BF2A-V5T2U4 Datasheet, PDF (19/39 Pages) Seiko Instruments Inc – CMOS VOLTAGE REGULATOR WITH RESET FUNCTION

FOR AUTOMOTIVE 125°C OPERATION HIGH-WITHSTAND VOLTAGE CMOS VOLTAGE REGULATOR WITH RESET FUNCTION
Rev.1.0_02
S-19311 Series
2. 2 Delay circuit
When the output voltage (VOUT) of the regulator rises under the status that "L" is output to the RO pin, the reset
release signal is output to the RO pin later than when VOUT becomes +VDET. The release delay time (trd) changes
according to CDLY. Refer to " Selection of Delay Time Adjustment Capacitor (CDLY)" for details.
Moreover, when VOUT decreases to −VDET or lower, the delay time of the same time length as the reset reaction
time (trr) occurs in the output to the RO pin. Refer to "2. Detector block" in " Explanation of Terms" for
details.
If the time period from when VOUT decreases to −VDET or lower to when VOUT increases to +VDET or higher is
significantly shorter compared to the length of trr, VDLY may not decrease to VDRL or lower. In that case, "H" output
remains in the RO pin.
Caution Since trd depends on the charge time of CDLY, trd may be shorter than the set value if the charge
operation is initiated under the condition that a residual electric charge is left in CDLY.
2. 3 Output circuit
The output form of the RO pin is Nch open-drain. The RO pin can output a signal without an external pull-up
resistor since it has a built-in resistor to pull up to the VOUT pin internally.
Do not connect to the pin other than VOUT pin when connecting an external pull-up resistor to the RO pin.
Caution Define the external pull-up resistance by sufficient evaluation including the temperature
characteristics under the actual usage conditions.
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