S-19311BF2A-V5T2U4 Datasheet, PDF (12/39 Pages) Seiko Instruments Inc – CMOS VOLTAGE REGULATOR WITH RESET FUNCTION

FOR AUTOMOTIVE 125°C OPERATION HIGH-WITHSTAND VOLTAGE CMOS VOLTAGE REGULATOR WITH RESET FUNCTION
S-19311 Series
Rev.1.0_02
 Condition of Application
Input capacitor (CIN)
Output capacitor (CL)
ESR of output capacitor
Delay time adjustment capacitor (CDLY)
External pull-up resistor (Rext)
: 2.2 μF or more
: 2.2 μF or more
: 10 Ω or less
: 1.0 nF or more
: 3 kΩ or more
Caution Generally a series regulator may cause oscillation, depending on the selection of external parts.
Confirm that no oscillation occurs in the application for which the above capacitors are used.
 Selection of Input and Output Capacitors (CIN, CL)
The S-19311 Series requires CL between the VOUT pin and the VSS pin for phase compensation. Operation is
stabilized by a ceramic capacitor with an output capacitance of 2.2 μF or more over the entire temperature range.
When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must be
2.2 μF or more, and the ESR must be 10 Ω or less.
The values of output overshoot and undershoot, which are transient response characteristics, vary depending on the
value of the output capacitor.
The required value of capacitance for the input capacitor differs depending on the application.
Caution Define the capacitance of CIN and CL by sufficient evaluation including the temperature
characteristics under the actual usage conditions.
 Selection of Delay Time Adjustment Capacitor (CDLY)
In the S-19311 Series, the delay time adjustment capacitor (CDLY) is necessary between the DLY pin and the VSS pin
to adjust the release delay time (trd) of the detector.
The set release delay time (trd(S)), is calculated by using following equation.
The release delay time (trd) at the time of the condition of CDLY = 47 nF is shown in " Electrical Characteristics".
trd(S) [ms] = trd [ms] ×
CDLY [nF]
47 [nF]
Caution 1. The above equation will not guarantee successful operation. Perform thorough evaluation including
the temperature characteristics using an actual application to set the constants.
2. Mounted board layout should be made in such a way that no current flows into or flows from the DLY
pin since the impedance of the DLY pin is high, otherwise correct delay time may not be provided.
3. Select CDLY whose leakage current can be ignored against the built-in constant current. The leakage
current may cause deviation in delay time and monitoring time. When the leakage current is larger
than the built-in constant current, no release takes place.
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