S-93L46A Datasheet, PDF (17/48 Pages) Seiko Instruments Inc – LOW VOLTAGE OPERATION CMOS SERIAL E2PROM

Rev.3.1_00
LOW VOLTAGE OPERATION CMOS SERIAL E²PROM
S-93L46A/56A/66A
4.5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and
then input the ERAL instruction and an address following the start bit. Any address can be input.
There is no need to input data. The chips erase operation starts when CS goes low. When the
clocks more than the specified number have been input, the clock pulse monitoring circuit cancels
the ERAL instruction. For details of the clock pulse monitoring circuit, refer to “„ Function to
Protect Against Write due to Erroneous Instruction Recognition”.
CS
t CDS
SK
1 2 3 4 5 6 7 89
Verify
Standby
DI
<1> 0
010
DO
4Xs
t SV
tHZ1
Busy _Ready
Hi-Z
t PR
Figure 17 Chip Erase Timing (S-93L46A)
CS
t CDS
SK
1 2 3 4 5 6 7 8 9 10 11
Verify
Standby
DI
<1> 0
010
6Xs
DO
t SV
Busy _Ready
tPR
tHZ1
Hi-Z
Figure 18 Chip Erase Timing (S-93L56A, S-93L66A)
Seiko Instruments Inc.
17