S-1133 Datasheet, PDF (17/37 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION AND LOW DROPOUT MIDDLE-OUTPUT CURRENT CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION AND LOW DROPOUT MIDDLE-OUTPUT CURRENT CMOS VOLTAGE REGULATOR
Rev.2.1_00
S-1133 Series
„ Operation
1. Basic operation
Figure 19 shows the block diagram of the S-1133 Series.
The error amplifier compares the reference voltage (V_ref) with V_fb, which is the output voltage resistance-divided by
feedback resistors R_s and R_f. It supplies the output transistor with the gate voltage necessary to ensure a certain
output voltage free of any fluctuations of input voltage and temperature.
VIN
Current
supply
Vref
Error
amplifier
−
+
Reference
voltage circuit
*1
Rf
Vfb
Rs
VOUT
VSS
*1. Parasitic diode
Figure 19
2. Output transistor
The S-1133 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due to inverse
current flowing from the VOUT pin through a parasitic diode to the VIN pin.
Seiko Instruments Inc.
17