S-19680AAAH-K8T2U Datasheet, PDF (16/27 Pages) Seiko Instruments Inc – Current consumption during operation

FOR AUTOMOTIVE 105°C OPERATION CURRENT MONITOR HIGH SIDE SWITCH
S-19680 Series
Rev.1.1_00
 Precautions
• The wiring patterns for the power supply and GND should be designed so that the impedance is low.
When mounting the input capacitor (C_IN) between the VDD pin and the VSS pin, and the output capacitor (C_L)
between the OUT pin and the VSS pin, connect them as close as possible to the respective destination pins of the
IC.
• The following use conditions are recommended to ensure stable operation of the S-19680 Series; however,
perform thorough evaluation including the temperature characteristics with an actual application to select C_IN and
C_L.
Input capacitor (C_IN): A ceramic capacitor with 0.1 μF or more is recommended.
Output capacitor (C_L): A ceramic capacitor with 0.1 μF or more is recommended.
• Wiring patterns on the application related to the VDD pin, the VIN pin and the SENSE pin should be designed so
that the impedance is low.
When mounting the shunt resistor (R_SHUNT) between the VDD pin and the VIN pin, and the sense resistor (R_SENSE)
between the VDD pin and SENSE pin, connect them as close as possible to the respective destination pins of the
IC. If capacitance is added to the SENSE pin, the current sense amplifier may oscillate, so caution should be
exercised.
• For R_SHUNT or R_SENSE, use the resistor with the following resistance. The values shown in " Electrical
Characteristics" are considered only the variation of the IC. In practice, R_SHUNT and R_SENSE variations also need to
be considered, so caution should be exercised.
Shunt resistor (R_SHUNT): 5.1 Ω
Sense resistor (R_SENSE): 5.1 kΩ
• When voltage of 3 V or higher is continuously applied between the VIN pin and SENSE pin, the current sense
amplifier characteristics may change, so caution should be exercised.
• If the OUT pin is steeply shorted with GND, a negative voltage exceeding the absolute maximum ratings may occur
in the OUT pin due to resonance phenomenon of the inductance and the capacitance including C_L on the
application. The resonance phenomenon is expected to be weakened by inserting a series resistance into the
resonance path, and the negative voltage is expected to be limited by inserting a protection diode between the
OUT pin and the VSS pin.
• Make sure of the conditions for the power supply voltage and the load current so that the internal loss does not
exceed the power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• SII Semiconductor Corporation claims no responsibility for any disputes arising out of or in connection with any
infringement by products including this IC of patents owned by a third party.
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