S-8211C Datasheet, PDF (15/41 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 1-CELL PACK

Rev.5.0_00
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211C Series
„ Test Circuits
Caution Unless otherwise specified, the output voltage levels “H” and “L” at CO pin (V_CO) and DO pin (V_DO) are
judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to
V_VM and the DO pin level with respect to V_SS.
(1) Overcharge Detection Voltage, Overcharge Release Voltage
(Test Condition 1, Test Circuit 1)
Overcharge detection voltage (V_CU) is defined as the voltage between the VDD pin and VSS pin at which V_CO goes
from “H” to “L” when the voltage V1 is gradually increased from the starting condition of V1 = 3.5 V. Overcharge
release voltage (V_CL) is defined as the voltage between the VDD pin and VSS pin at which V_CO goes from “L” to “H”
when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (V_HC) is defined as the difference
between overcharge detection voltage (V_CU) and overcharge release voltage (V_CL).
(2) Overdischarge Detection Voltage, Overdischarge Release Voltage
(Test Condition 2, Test Circuit 2)
Overdischarge detection voltage (V_DL) is defined as the voltage between the VDD pin and VSS pin at which V_DO goes
from “H” to “L” when the voltage V1 is gradually decreased from the starting condition of V1 = 3.5 V, V2 = 0 V.
Overdischarge release voltage (V_DU) is defined as the voltage between the VDD pin and VSS pin at which V_DO goes
from “L” to “H” when the voltage V1 is then gradually increased. Overdischarge hysteresis voltage (V_HD) is defined as
the difference between overdischarge release voltage (V_DU) and overdischarge detection voltage (V_DL).
(3) Discharge Overcurrent Detection Voltage
(Test Condition 3, Test Circuit 2)
Discharge overcurrent detection voltage (V_DIOV) is defined as the voltage between the VM pin and VSS pin whose
delay time for changing V_DO from “H” to “L” lies between the minimum and the maximum value of discharge
overcurrent delay time when the voltage V2 is increased rapidly (within 10 µs) from the starting condition of
V1 = 3.5 V, V2 = 0 V.
(4) Load Short-circuiting Detection Voltage
(Test Condition 3, Test Circuit 2)
Load short-circuiting detection voltage (V_SHORT) is defined as the voltage between the VM pin and VSS pin whose
delay time for changing V_DO from “H” to “L” lies between the minimum and the maximum value of load short-circuiting
delay time when the voltage V2 is increased rapidly (within 10 µs) from the starting condition of V1 = 3.5 V, V2 = 0 V.
(5) Charge Overcurrent Detection Voltage
(Test Condition 4, Test Circuit 2)
Charge overcurrent detection voltage (V_CIOV) is defined as the voltage between the VM pin and VSS pin whose delay
time for changing V_CO from “H” to “L” lies between the minimum and the maximum value of charge overcurrent delay
time when the voltage V2 is decreased rapidly (within 10 µs) from the starting condition of V1 = 3.5 V, V2 = 0 V.
(6) Operating Current Consumption
(Test Condition 5, Test Circuit 2)
The operating current consumption (I_OPE) is the current that flows through the VDD pin (I_DD) under the set conditions
of V1 = 3.5 V and V2 = 0 V (normal status).
Seiko Instruments Inc.
15