S-11L10 Datasheet, PDF (14/35 Pages) Seiko Instruments Inc – SUPER-LOW OUTPUT LOW DROPOUT CMOS VOLTAGE REGULATOR

SUPER-LOW OUTPUT VOLTAGE LOW DROPOUT CMOS VOLTAGE REGULATOR
S-11L10 Series
Rev.1.0_00
„ Operation
1. Basic operation
Figure 13 shows the block diagram of S-11L10 Series.
The error amplifier compares the reference voltage (V_ref) with V_fb, which is the output voltage resistance-divided by
feedback resistors R_s and R_f. It supplies the gate voltage necessary to maintain the constant output voltage which is
not influenced by the input voltage and temperature change, to the output transistor.
VIN
Current
supply
V_ref
Error
amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 13
2. Output transistor
In the S-11L10 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due to inverse
current flowing from the VOUT pin through a parasitic diode to the VIN pin.
14
Seiko Instruments Inc.