S-1132 Datasheet, PDF (14/35 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR
S-1132 Series
Rev.3.2_00
3. Shutdown pin (ON/OFF pin)
This pin starts and stops the regulator.
When the ON/OFF pin is set to the shutdown level, the operation of all internal circuits stops, and the built-in P-channel
MOS FET output transistor between the VIN pin and VOUT pin is turned off to substantially reduce the current
consumption. The VOUT pin becomes the V_SS level due to the internally divided resistance of several hundreds kΩ
between the VOUT pin and VSS pin.
The structure of the ON/OFF pin is as shown in Figure 14. Since the ON/OFF pin is neither pulled down nor pulled up
internally, do not use it in the floating state. In addition, note that the current consumption increases if a voltage of 0.3
V to V_IN – 0.3 V is applied to the ON/OFF pin. When the ON/OFF pin is not used, connect it to the VSS pin if the logic
type is “A” and to the VIN pin if it is “B”.
Table 7
Logic Type
A
A
B
B
ON/OFF Pin
“L”: Power on
“H”: Power off
“L”: Power off
“H”: Power on
Internal Circuits
Operating
Stopped
Stopped
Operating
VOUT Pin Voltage
Set value
V_SS level
V_SS level
Set value
Current Consumption
I_SS1
I_SS2
I_SS2
I_SS1
VIN
ON/OFF
VSS
Figure 14
14
Seiko Instruments Inc.