S-1132 Datasheet, PDF (10/35 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR
S-1132 Series
Rev.3.2_00
„ Standard Circuit
INPUT
C_IN^*1
VIN
VOUT
ON/OFF
VSS
OUTPUT
C_L^*2
Single GND
GND
*1. C_IN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 0.1 µF or more can be used for C_L.
Figure 11
Caution The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
„ Application Conditions
Input capacitor (C_IN):
Output capacitor (C_L):
ESR of output capacitor:
0.1 µF or more
0.1 µF or more
2.0 Ω or less
Caution A general series regulator may oscillate, depending on the external components selected. Check
that no oscillation occurs with the application using the above capacitor.
„ Selection of Input and Output Capacitors (C_IN, C_L)
The S-1132 Series requires an output capacitor between the VOUT and VSS pins for phase compensation. Operation is
stabilized by a ceramic capacitor with an output capacitance of 0.1 µF or more in the entire temperature range. However,
when using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, a ceramic capacitor with a capacitance
of 0.1 µF or more and an ESR of 2.0 Ω or less is required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output capacitor.
The required capacitance of the input capacitor differs depending on the application.
The recommended value for an application is 0.1 µF or more for C_IN and 0.1 µF or more for C_L; however, when selecting the
output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual device.
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Seiko Instruments Inc.