S1167 Datasheet, PDF (13/31 Pages) Seiko Instruments Inc – ULTRA LOW CURRENT CONSUMPTION, HIGH RIPPLE REJECTION

ULTRA LOW CURRENT CONSUMPTION, HIGH RIPPLE REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.3.2_00
S-1167 Series
 Operation
1. Basic Operation
Figure 12 shows the block diagram of the S-1167 Series.
The error amplifier compares the reference voltage (V_ref) with feedback voltage (V_fb), which is the output voltage
resistance-divided by feedback resistors (R_s and R_f). It supplies the gate voltage necessary to maintain the constant
output voltage which is not influenced by the input voltage and temperature change, to the output transistor.
VIN
Current
supply
V_ref
Error
amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 12
2. Output Transistor
In the S-1167 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due to reverse
current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of V_OUT became higher
than V_IN.
Seiko Instruments Inc.
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