S1167 Datasheet, PDF (10/31 Pages) Seiko Instruments Inc – ULTRA LOW CURRENT CONSUMPTION, HIGH RIPPLE REJECTION

ULTRA LOW CURRENT CONSUMPTION, HIGH RIPPLE REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1167 Series
Rev.3.2_00
 Standard Circuit
Input
C_IN^*1
VIN
VOUT
ON / OFF
VSS
Output
C_L^*2
Single GND
GND
*1. A capacitor for stabilizing the input.
*2. A ceramic capacitor of 1.0 μF or more can be used.
Figure 10
Caution The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
 Condition of Application
Input capacitor (C_IN): 1.0 μF or more
Output capacitor (C_L): 1.0 μF or more
Equivalent series resistance (R_ESR) of output capacitor: 1.0 Ω or less
Caution Generally a series regulator may cause oscillation, depending on the selection of external parts.
Check that no oscillation occurs with the application using the above capacitor.
 Selection of Input Capacitor (C_IN) and Output Capacitor (C_L)
The S-1167 Series requires an output capacitor between the VOUT pin and the VSS pin for phase compensation.
Operation is stabilized by a ceramic capacitor with an output capacitance of 1.0 μF or more in the entire temperature
range. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance
must be 1.0 μF or more, and an equivalent series resistance (R_ESR) must be 1.0 Ω or less.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor. The required capacitance of the input capacitor differs depending on the application.
The recommended value for an application is C_IN ≥ 1.0 μF, C_L ≥ 1.0 μF; however, when selecting the output
capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual device.
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Seiko Instruments Inc.