S-8230AAD-I6T1U Datasheet, PDF (12/37 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK
S-8230A/B Series
Rev.2.5_00
16. CTL pin voltage "H", CTL pin voltage "L"
(Test circuit 2)
16. 1 CTL pin control logic active "H"
The CTL pin voltage "H" (V_CTLH) is defined as the voltage V5 at which V_DO goes from "H" to "L" when the voltage
V5 is gradually increased under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V. After that, the CTL pin voltage "L"
(V_CTLL) is defined as the voltage V5 at which V_DO goes from "L" to "H" after V5 is gradually decreased.
16. 2 CTL pin control logic active "L"
The CTL pin voltage "L" (V_CTLL) is defined as the voltage difference between the voltage V5 and the voltage V1
(V1 − V5) at which V_DO goes from "H" to "L" when the voltage V5 is gradually increased under the set conditions of
V1 = 3.4 V, V2 = V5 = 0 V. After that, the CTL pin voltage "H" (V_CTLH) is defined as the voltage difference between
V1 − V5 at which V_DO goes from "L" to "H" after V5 is gradually decreased.
17. Overcharge detection delay time
(Test circuit 5)
The overcharge detection delay time (t_CU) is the time needed for V_CO to go to "L" after the voltage V1 increases and
exceeds V_CU under the set condition of V1 = 3.4 V, V2 = V5 = 0 V.
18. Overdischarge detection delay time
(Test circuit 5)
The overdischarge detection delay time (t_DL) is the time needed for V_DO to go to "L" after the voltage V1 decreases
and falls below V_DL under the set condition of V1 = 3.4 V, V2 = V5 = 0 V.
19. Discharge overcurrent detection delay time
(Test circuit 5)
t_DIOV is the time needed for V_DO to go to "L" after the voltage V2 increases and exceeds V_DIOV under the set
conditions of V1 = 3.4 V, V2 = V5 = 0 V.
20. Load short-circuiting detection delay time
(Test circuit 5)
t_SHORT is the time needed for V_DO to go to "L" after the voltage V2 increases and exceeds V_SHORT under the set
conditions of V1 = 3.4 V, V2 = V5 = 0 V.
21. Charge overcurrent detection delay time
(Test circuit 5)
t_CIOV is the time needed for V_CO to go to "L" after the voltage V2 decreases and falls below V_CIOV under the set
condition of V1 = 3.4 V, V2 = V5 = 0 V.
22. Discharge inhibition delay time
(Test circuit 5)
22. 1 CTL pin control logic active "H"
Discharge inhibition delay time (t_CTL) is the time needed for V_DO to go to "L" after the voltage V5 increases
and exceeds V_CTLH under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V.
22. 2 CTL pin control logic active "L"
Discharge inhibition delay time (t_CTL) is the time needed for V_DO to go to "L" after the voltage V5 increases
and V1 − V5 falls below V_CTLL under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V.
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