SDA9270 Datasheet, PDF (9/33 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics

SDA 9270
2.1 Input Data Format
The SDA 9270 accepts for the input channels A and B two different input formats
(I²C-Bus : INFOR) with two possible sample frequency relations of Y : (B-Y) : (R-Y). The
representation of the samples is programmable separately for luminance and
chrominance signals as positive dual code or 2’s complement code (I²C-Bus : INCODL,
INCODC)
Data
Pin
Yx7
Yx6
Yx5
Yx4
Yx3
Yx2
Yx1
Yx0
UVx7
UVx6
UVx5
UVx4
UVx3
UVx2
UVx1
UVx0
Data Format 4:1:1
INFOR = 0
Y₀₇ Y₁₇ Y₂₇ Y₃₇
Y₀₆ Y₁₆ Y₂₆ Y₃₆
Y₀₅ Y₁₅ Y₂₅ Y₃₅
Y₀₄ Y₁₄ Y₂₄ Y₃₄
Y₀₃ Y₁₃ Y₂₃ Y₃₃
Y₀₂ Y₁₂ Y₂₂ Y₃₂
Y₀₁ Y₁₁ Y₂₁ Y₃₁
Y₀₀ Y₁₀ Y₂₀ Y₃₀
U₀₇ U₀₅ U₀₃ U₀₁
U₀₆ U₀₄ U₀₂ U₀₀
V₀₇ V₀₅ V₀₃ V₀₁
V₀₆ V₀₄ V₀₂ V₀₀
4:2:2 Parallel
INFOR = 1
Y₀₇
Y₁₇
Y₀₆
Y₁₆
Y₀₅
Y₁₅
Y₀₄
Y₁₄
Y₀₃
Y₁₃
Y₀₂
Y₁₂
Y₀₁
Y₁₁
Y₀₀
Y₁₀
U₀₇
V₀₇
U₀₆
V₀₆
U₀₅
V₀₅
U₀₄
V₀₄
U₀₃
V₀₃
U₀₂
V₀₂
U₀₁
V₀₁
U₀₀
V₀₀
Yx,UVx : x : A,B
X_ab:
X: signal component
a: sample number
b: bit number
The amplitude resolution for each input signal component is 8 bit, the maximum clock
frequency is 30 MHz. Consequently the SDA 9270 is dedicated for applications in high
quality digital video systems. The data input stages and the internal data multiplexer
operate with a special input clock (SCA). For applications in the Siemens MEGAVISION
System the SCA-clock is identical with the memory output clock.
Semiconductor Group
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