SDA9270 Datasheet, PDF (12/33 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics

SDA 9270
A second 25 Hz frame sync signal is needed in the interpolation and switching block and
in the VS3 pulse generation block for assuring an output data sequence of the channel
Q synchronized with the VS3 pulse. As reference signals for this second frame sync
signal are used the 100 Hz vertical sync signal VS2 and the blanking signal BLN2 both
generated by the MSC SDA 9220.
2.7 SYNC-Signal Generation
This functional block generates a couple of sync signal needed in the processing stages
following the Field Mixer device. This couple includes the vertical sync signal VS3 and
the horizontal blanking signal BLN3. All these signals are synchronized with the output
channel Q.
2.8 I²C-Bus
2.8.1 I²C-Bus Address
0001111
2.8.2 I²C-Bus Format
write:
S 0 0 0 1 1 1 1 0 A Subaddress A
Data Byte
S: Start condition
A: Acknowledge
P: Stop condition
NA: Not Acknowledge
An automatical address increment function is implemented.
A _*****
AP
Semiconductor Group
12