SDA9188-3X Datasheet, PDF (7/31 Pages) Siemens Semiconductor Group – Picture-in-Picture Processor with On-Chip PLL

SDA 9188-3X
During the decimation process the following parts of the original picture are processed:
1. DECHOR/DECVER = 0(1/9-Picture)
during 625 line mode:
during 525 line mode:
2. SIZE = 1(1/16-Picture):
during 625 line mode:
during 525 line mode:
Line 36 … 302; Pixel 13 … 636
Line 26 … 256; Pixel 13 … 636
Line 36 … 303; Pixel 17 … 640
Line 26 … 257; Pixel 17 … 640
Temporary Storage of Inset Picture
The PIP memory has a capacity of 169.812 bits. The memory organisation is 89 × 212 × 9 bits.
Data are written in with the inset and read out with the parent clock frequency.
For standard video signals with 50 or 60 Hz a full frame display is possible. To assure a correct
display of the two fields, the control of the memory is done dependendly of the field and the phase
relation of the Inset and Parent channel. Frame mode display is only possible for standard 50 Hz/
60 Hz video signals. Certain VCR-functions (e.g. fast forward-mode), non interlaced signals and
50 Hz/60 Hz mixed-mode would cause inacceptable picture distortions. Under these conditions the
SDA 9188-3X switches automatically into field mode display.
Also freezed pictures can only be displayed in the field-mode.
Output of Data in Parent Window
The four corners of the parent picture are foreseen as positions for inserting the inset picture. To
enable compatibility to different system configurations, readout from memory can be shifted
horizontally in 63 steps by max. 252 LL3P cycles and vertically in 15 steps by max. 30 lines in the
parent field setting the control bits RDH and RDV in control register 2 and 3.
The coordinates BRP, BRL of the normal location of all four insertion positions are given in table 3
for RDH = RDV = 8.
The SELECT signal goes high during the display of the inset picture. Outside of the inset picture
SELECT signal is low and the analog outputs OUT1-OUT3 provide the black level. The external
wiring can produce a delay between the SELECT signal and the analog outputs. This delay can be
compensated by bits SD0-SD2 in register 2 via the I²C bus.
A frame with one of eight colors can be inserted using control bits FRON, COL0-2. The width of the
frame is fixed by FRWV at three or two lines and by FRWH at six or four pixels. The brightness can
be adjusted in 16 stages.
Semiconductor Group
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