SDA9188-3X Datasheet, PDF (18/31 Pages) Siemens Semiconductor Group – Picture-in-Picture Processor with On-Chip PLL

SDA 9188-3X
Register 7 (Address 07_H)
Bit
d4:d0
Function
Delay of the VSP pulse
d5
0 = Vertical noise reduction OFF
1 = Vertical noise reduction ON
d6
0 = Check for correct TV standard inactive
1 = Check for correct TV standard active
d7
0 = PAL/NTSC
1 = SECAM
Name Remarks
VSPDEL
Setting is possible in steps
of 2,37 µs (50 Hz or
1,185 µs 100 Hz)
(see measuring circuit 6)
VSPIS
STATP
Noise reduction for the
vertical pulse of the parent
channel (should be set to
‘1’ under normal
conditions).
If the check for the correct
TV standard is active a full
frame display is only
possible if the number of
lines is exactly according
the TV standard:
312.5 (50 Hz)
262.5 (60 Hz)
AMSEC
Doubling of the gain if a
sufficient SECAM decoder
without delay line is used
Register 8 (Address 08_H)
Bit
d3:d0
Function
0000 = min. brightness of the border frame
1111 = max. brightness of the border frame
Name
FRY5:2
Remarks
Setting only valid if the bit
d4 is set to ‘1’
d4
0 = brightness of the border frame can be FRYEN
selected by FRY
1 = brightness of the border frame can be
selected by FRY5:2
d7:d5 not used to be set to “0“.
Semiconductor Group
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