SDA9188-3X Datasheet, PDF (11/31 Pages) Siemens Semiconductor Group – Picture-in-Picture Processor with On-Chip PLL

SDA 9188-3X
I²C BUS
Organization of I²C Bus Registers
SDA 9188-3X has the device address
00101110 = 2E_H
Applying the supply voltage V_DD produces a power-up reset. The bus lines SDA and SCL are
enabled. All bits in the registers except bit PL27 (D3 in Register 0) are set to 0. Bit PL27 is set to 1.
The I²C bus interface works as a slave receiver and only functions if the inset clock LL3I is available.
Write Operation
S 0010 1110 A
0000 XXXX A
XXXX XXXX A
P
↑
↑
→ ^Ack
W^wrrⁱi^tt^ee
↑
Start
Stop
Chip address byte
Register address
Data word1
After writing a byte into any register, the register address is automatically incremented for the write
access to the next register.
The following table shows the functions that can be set on the I²C bus and define the data bytes. Not
used data bits have to be written with “0“ . Before PON = 1 all other bits have to be defined in
relation to the used hardware.
Function
CONTROL 0
CONTROL 1
CONTROL 2
CONTROL 3
CONTROL 4
CONTROL 5
CONTROL 6
CONTROL 7
CONTROL 8
CONTROL 9
SUB-
address _D7
D6
00
0
0
01
0
0
02
0
SD2
03
POS 1 POS 0
04
CON0
CON1
05
DECVER DECHOR
06
FRAME STATI
07
AMSEC STATP
08
0
0
09
0
PLLTC
D5
STILL
0
SD1
RDH 5
CON2
FRWV
VSIIS
VSPIS
0
SOS
D4
D3
D2
D1
D0
SIZE
PL27
NINT
OUT
PON
FRY
COL2
COL1
COL0
FRON
SD0
RDV 3 RDV 2 RDV 1 RDV 0
RDH 4 RDH 3 RDH 2 RDH 1 RDH 0
CON3
0
SOP PLLOFF HSP5
FRWH PMOD1 PMOD0 IMOD1 IMOD0
VSIDEL4 VSIDEL3 VSIDEL2 VSIDEL1 VSIDEL0
VSPDEL4 VSPDEL3 VSPDEL2 VSPDEL1 VSPDEL0
FRYEN FRY5
FRY4
FRY3
FRY2
VCOSEL3 VCOSEL2 VCOSEL1 VCOSEL0
0
Table 6: I²C Bus Register
The bits are numbered in the reverse order to the data stream of the I²C bus.
If the control software addresses the internal register number 8 or 9 there is no longer any software
compatibility to the devices SDA 9088-2 and SDA 9089X. This is caused by the fact that in these
devices register 0 and 1 can also be accessed via the subaddress 08 and 09.
Semiconductor Group
11