HYB314171BJ-50- Datasheet, PDF (7/24 Pages) Siemens Semiconductor Group – 3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh

HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
AC Characteristics ⁵⁾⁶⁾
T_A = 0 to 70 °C; V_SS = 0 V; V_CC = 3.3 V ± 0.3 V, t_T = 5 ns
Parameter
Symbol
Limit Values
Unit Note
-50
- 60
- 70
min. max. min. max. min. max.
Common Parameters
Random read or write cycle time t_RC
RAS precharge time
t_RP
RAS pulse width
t_RAS
CAS pulse width
t_CAS
Row address setup time
t_ASR
Row address hold time
t_RAH
Column address setup time
t_ASC
Column address hold time
t_CAH
RAS to CAS delay time
t_RCD
RAS to column address delay
t_RAD
time
RAS hold time
t_RSH
CAS hold time
t_CSH
CAS to RAS precharge time
t_CRP
Transition time (rise and fall)
t_T
Refresh period
t_REF
Refresh period (L-version)
t_REF
95 –
110 –
130 –
ns
35 –
40 –
50 –
ns
50 10k 60 10k 70 10k ns
15 10k 15 10k 20 10k ns
0
–
0
–
0
–
ns
10 –
10 –
10 –
ns
0
–
0
–
0
–
ns
10 –
15 –
15 –
ns
20 35 20 45 20 50 ns
15 25 15 30 15 35 ns
15 –
15 –
20 –
ns
50 –
60 –
70 –
ns
5
–
5
–
5
–
ns
3 50 3 50 3 50 ns 7
– 16 – 16 – 16 ms
– 128 – 128 – 128 ms
Read Cycle
Access time from RAS
t_RAC
Access time from CAS
t_CAC
Access time from column address t_AA
OE access time
t_OEA
Column address to RAS lead time t_RAL
Read command setup time
t_RCS
Read command hold time
t_RCH
Read command hold time ref. to t_RRH
RAS
CAS to output inlow-Z
t_CLZ
–
50 –
60 –
70 ns 8, 9
–
15 –
15 –
20 ns 8, 9
–
25 –
30 –
35 ns 8,10
– 15 – 15 – 20 ns
25 –
30 –
35 –
ns
0
–
0
–
0
–
ns
0
–
0
–
0
–
ns 11
0
–
0
–
0
–
ns 11
0
–
0
–
0
–
ns 8
Semiconductor Group
7